A digital chip timing recovery loop for band-limited direct-sequence spread-spectrum signals

Migration towards a full-digital implementation of modems is currently one of the main trends in transmission systems design. In this paper we describe a non coherent a11digital delay lock loop (DDLL) suited for chip timing synchronization in band-limited direct sequence spread spectrum (DS/SS) systems, and we thoroughly analyze its performance. The key features of this novel scheme are represented by its low-complexity processing section together with its good tracking capability. Analytical expressions for the DDLL S-curve and steady-state timing jitter are derived and confirmed by a timedomain computer simulation. Furthermore, the Mean Time to Lose Lock (MTLL) of the loop is evaluated and some numerical results are reported. The proposed chip timing synchronization scheme reveals also an improved tracking performance when compared to the traditional analog DLL for rectangular chip DS/SS signals.